This application is based on Japanese Patent Application No. 10-124367, filed May 7, 1998, Japanese Patent Application No. 10-203454, filed Jul. 17, 1998, and U.S. Pat. application Ser. No. 09/305,752, filed May 6, 1999, the contents of which are incorporated herein by reference.
The present invention relates to a semiconductor memory for configuring SDRAM (Synchronous DRAM) which needs to operate at a high-speed, and more particularly high-speed cycle clock-synchronous memory and memory system using the same.
SDRAM has banks comprising, for example, a plurality of memory cell arrays (referred to as "cell array" below). A sense amplifier zone in each back is shared by cell arrays adjacent thereto. Configuration of such a sense amplifier area is allowed to reduce an area occupied by the same. Also, an input/output data line may be shared by each cell array. Data is transferred to a buffer for output data burst via such shared data lines.
When data in an arbitrary cell array is accessed, all of cell arrays in the bank including the accessed cell array are controlled all at once. That is, a word line (WL) in an arbitrary cell array to be accessed is activated to be an active level, and data of each memory cell belonging to this WL is temporally stored by each sense amplifier.
Thereafter, an arbitrary data is read out via an input/output data line. Data of each memory cell belonging to the above-mentioned word line WL is restored. After the WL is set at an inactive level, a bit line and the sense amplifier are equalized. Then, an arbitrary cell array in the bank can be subjected to the next activation.
FIG. 14 is a timing chart showing an example of data access design, according to the prior art described above. /RAS (Row Address Strobe) signal (the leading "P, is capped with a horizontal bar in drawings) makes a word line of a selected cell array active level during "L" (low level). As a result, it becomes possible to access data in each memory cell belonging to the selected WL, that is, the page data.
A value of address (Add) at the time when /RAS signal falls to "L1" designates a cell array and a word line (WL) to be selected (as denoted by (R)). Thereafter, each time /CAS (Column Address Strobe) signal (the leading "P, is capped with a horizontal bar in drawings)falls down, page address is determined (as denoted by (C1) to (C4)). Accordingly, data is output from a sense amplifier in a column corresponding to the page address.
For internal operation, during a period in which /RAS is set at "L", data in each memory cell belonging to the word line WL in the activated cell array is kept in the state of sense, amplified (stored condition) and restore state (S&R). EQL is equalizing operation of a bit line and a sense amplifier. EQL functions after /RAS becomes "H" (high level) and the word line WL becomes an inactive level.
Such data access operation enables a high-speed access to data in a memory cell belonging to selected one word line WL. However, such high-speed access as mentioned above cannot be kept when selection of the WL is frequently changed. This is because access to a column cannot be performed until selection of a new word line becomes possible.
Regarding access to data in cell arrays in the same bank, an attention should be paid to a time from completion of selecting one word line WL1 until it is possible to select another word line WL2.
Selection of the word line WL2 is prohibited until EQL of the internal operation in FIG. 14 is terminated, regardless of the memory cell that the WL2 belongs to. Here, EQL means equalization of the bit line and the sense amplifier concerning to the preceding data access to the word line WL1. Thus, it always takes a fixed and long time to access from a different word line in the same bank.
In general, as well known, DRAM senses data by using a ratio of a cell capacitance and a bit line capacitance to each other. Therefore, it should be considered that a memory is configured to ensure cell capacitor for sensing cell data and to provide a high-speed sense operation. It is preferable to make the number of cells belonging to a bit line connected to one sense amplifier as small as possible. And it is also preferable to reduce the number of cells connected to one word line in order to decrease RC delay time needed as a rise time and a fall time of a word line.
In other words, in view of functional improvement of a memory, a size of a cell array comprising a plurality of memory cells cannot be so large. Therefore, it is preferable to divide a memory into a number of cell arrays.
In a design of a memory, sense amplifiers are shared by adjacent cell arrays. Thus, the area occupied by the sense amplifier becomes half of that in case of not being shared. Such a shared sense amplifier, however, enables only one of the adjacent cell arrays to use the same at a single access.
In recent years, there has been employed a UMA (Unified memory Architecture) in which a single memory is data-accessed by many equipment. By employing a UMA, access to word lines has been changed frequently. As a result, according to the prior art, an unnecessary waiting time during data transfer often occurs. Therefore, such a conventional system needs an improvement for more efficient use of memory data.